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july 2012 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 fxmar2104 ? dual-supply, 4-bit voltag e translator / isolator for open-d rain and push-pull applications fxmar2104 dual-supply, 4-bit voltage translator / isolator for open-drain and push-pull applications features ? bi-directional interface between any two levels: 1.65v to 5.5v ? direction control not needed ? internal 10k pull-up resistors ? system gpio resources not required when oe tied to v cca ? i 2 c-bus ? isolation ? a/b port v ol = 175mv (typical), v il = 150mv, i ol = 6ma ? open-drain inputs / outputs ? works in a push-pull environment ? accommodates standard-mode and fast-mode i 2 c-bus devices ? supports i 2 c clock stretching & multi-master ? fully configurable: inputs and outputs track v cc ? non-preferential power-up; either v cc may be powered-up first ? outputs switch to 3-state if either v cc is at gnd ? tolerant output enable: 5v ? packaged in 12-lead ultrathin mlp (1.8mm x 1.8mm) ? esd protection exceeds: - 5kv hbm (per jesd22-a114) - 2kv cdm (per jesd22-c101) description the fxmar2104 is a 4-bit high-performance, configurable dual-voltage supply, open-drain translator for bi-directional voltage translation over a wide range of input and output voltages levels. the fxmar2104 also works in a push-pull environment. intended for use as a voltage translator in applications using the i 2 c-bus ? interface, the input and output voltage levels are compatible with i 2 c device specification voltage levels. eight internal 10k pull-up resistors are integrated. the device is designed so t hat the a port tracks the v cca level and the b port tracks the v ccb level. this allows for bi-directional a/b port voltage translation between any two levels from 1.65v to 5.5v. v cca can equal v ccb from 1.65v to 5.5v. non-preferential power-up means v cc can be powered- up first. internal power-down control circuits place the device in 3-state if either v cc is removed. the two ports of the devic e have automatic direction- sense capability. either port may sense an input signal and transfer it as an output signal to the other port. ordering information part number operating temperature range top mark package packing method FXMAR2104UMX -40 to +85c by 12-l ead, ultrathin mlp, 1.8mm x 1.8mm 5000 units on tape and reel
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 2 fxmar2104 ? dual-supply, 4-bit voltage translator / isolator / for open-d rain and push-pull applications block diagram figure 1. block diagram, 1 of 4 channels v ccb v cca a b oe dynamic drive r ( with time out) dynamic drive r (with time out ) v bias a v bias b internal direction generato r & control internal direction generato r & control 10k 10k
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 3 fxmar2104 ? dual-supply, 4-bit voltage translator / isolator / for open-d rain and push-pull applications pin configuration figure 2. umlp (top-through view) pin definitions pin # name description 1 v ccb b-side power supply 2 v cca a-side power supply 3, 4, 5, 6 a 0 , a 1, a 2 , a 3 a-side inputs or 3-state outputs 7 gnd ground 8 oe output enable input 9, 10, 11, 12 b 3 , b 2, b 1 , b 0 b-side inputs or 3-state outputs truth table control outputs oe low logic level 3-state high logic level normal operation note: 1. if the oe pin is driven low, the fxmar2104 is disabled and the a 0 , a 1 , a 2 , a 3 , b 0 , b 1 , b 2 and b 3 pins (including dynamic drivers) are forced into 3-state. also , if the oe pin is driven low, all eight 10k internal pull-up resistors are decoupled from their respective v cc s.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 4 fxmar2104 ? dual-supply, 4-bit voltage translator / isolator / for open-d rain and push-pull applications absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cca , v ccb supply voltage -0.5 7.0 v v in dc input voltage a port -0.5 7.0 b port -0.5 7.0 control input (oe) -0.5 7.0 v o output voltage (2) a n outputs 3-state -0.5 7.0 v b n outputs 3-state -0.5 7.0 a n outputs active -0.5 v cca + 0.5v b n outputs active -0.5 v ccb + 0.5v i ik dc input diode current at v in < 0v -50 ma i ok dc output diode current at v o < 0v -50 ma at v o > v cc +50 i oh / i ol dc output source/sink current -50 +50 ma i cc dc v cc or ground current per supply pin 100 ma p d power dissipation at 400khz 0.129 mw t stg storage temperature range -65 +150 c esd electrostatic discharge capability human body model, b-port (vs. gnd & vs. v ccb ) 8 kv human body model, all pins, jesd22-a114 5 charged device mode, jesd22-c101 2 note: 2. i o absolute maximum rating must be observed. recommended operating conditions the recommended operating conditions table defines th e conditions for actual device operation. recommended operating conditions are specified to en sure optimal performance to the datash eet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. units v cca , v ccb power supply operating 1.65 5.50 v v in input voltage a port 0 5.5 v b port 0 5.5 control input (oe) 0 v cca ja thermal resistance 301.5 c/w t a free air operating temperature -40 +85 c note: 3. all unused i/o pins should be disconnected.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 5 fxmar2104 ? dual-supply, 4-bit voltage translator / isolator / for open-d rain and push-pull applications functional description power-up/power-down sequencing fxm translators offer an advantage in that either v cc may be powered up first. this benefit derives from the chip design. when either v cc is at 0v, outputs are in a high-impedance state. the control input (oe) is designed to track the v cca supply. a pull-down resistor tying oe to gnd should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up/power-down. the size of the pull- down resistor is based upon the current-sinking capability of the device driving the oe pin. the recommended power-up sequence is: 1. apply power to the first v cc . 2. apply power to the second v cc . 3. drive the oe input high to enable the device. the recommended power-down sequence is: 1. drive oe input low to disable the device. 2. remove power from either v cc . 3. remove power from other v cc . note: 4. alternatively, the oe pin can be hardwired to v cca to save gpio pins. if oe is hardwired to v cca , either v cc can be powered up or down first. application circuit figure 3. application circuit
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 6 fxmar2104 ? dual-supply, 4-bit voltage translator / isolator / for open-d rain and push-pull applications application information the fxmar2104 has four bi-directional, open-drain i/os and includes a total of eight internal 10k ? pull-up resistors (rpus) on each port of all four data i/o pins. if a pair of data i/o pins (a n /b n ) is not used, these pins should be left unconnected, eliminating unwanted current flow through the internal rpus. external rpus can be added to the i/os to reduce the total rpu value, depending on the total bus capacitance. the user is free to lower the total pull-up resistor value to meet the maximum i 2 c edge rate per the i 2 c specification (um10204 rev. 03, june 19, 2007). for example, according to the i 2 c specification, the maximum edge rate (30% - 70%) during fast mode (400kbit/s) is 300ns. if the bus capacitance is approaching the maximum 400pf, a lower total rpu value helps keep the rise time below 300ns (fast mode). likewise, the i 2 c specification also specifies a minimum scl high time of 600ns during fast mode (400khz). lowering the total rpu also helps increase the scl high time. if the bus capacitance approaches 400pf, consider the fxma2102, which does not contain internal rpus. then the user can calculate the ideal external rpu value. section 7.1 of the i 2 c specification provides an excellent guideline for pull-up resistor sizing. theory of operation the fxmar2104 is designed for high-performance level shifting and buffer / repeating in an i 2 c application. figure 1 shows that each bi-directional channel contains two series-npassgates and two dynamic drivers. this hybrid architecture is highly beneficial in an i 2 c application where auto-direction is a necessity. for example, during the following three i 2 c protocol events: ? clock stretching ? slave?s ack bit (9 th bit = 0) following a master?s write bit (8 th bit = 0) ? clock synchronization and multi master arbitration the bus direction needs to change from master-to-slave to slave to master without the occurrence of an edge. if there is an i 2 c translator between the master and slave in these examples, the i 2 c translator must change direction when both a and b ports are low. the npassgates can accomplish this task very efficiently because, when both a and b ports are low, the npassgates act as a low resistive short between the two (a and b) ports. due to i 2 c?s open-drain topology, i 2 c masters and slaves are not push-pull driv ers. logic lows are ?pulled down? (i sink ), while logic highs are ?let go? (3-state). for example, when the master lets go of scl (scl always comes from the master), the rise time of scl is largely determined by the rc time constant, where r = r pu and c = the bus capacitance. if th e fxmar2104 is attached to the master [on the a port] and there is a slave on the b port, the npassgates act as a low resistive short between the ports until either of the port?s v cc /2 thresholds are reached. after the rc time constant has reached the v cc /2 threshold of either port, the port?s edge detector triggers both dynamic drivers to drive their respective ports in the low-to-high (lh) direction, accelerating the rising edge. the resulting rise time resembles the scope shot in figure 4. effectively, two distinct slew rates appear in rise time. the first slew rate (slower) is the rc time constant of the bus. the second slew rate (much faster) is the dynamic driver accelerating the edge. if both the a and b ports of the translator are high, a high-impedance path exists between the a and b ports because both the n passgates are turn ed off. if a master or slave device decides to pull scl or sda low, that device?s driver pulls down (i sink ) scl or sda until the edge reaches the a or b port v cc /2 threshold. when either the a or b port threshold is reached, the port?s edge detector triggers both dynamic drivers to drive their respective ports in the high-to-low (hl) direction, accelerating the falling edge. figure 4. waveform c: 600pf, total r pu : 2.2k
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 7 fxmar2104 ? dual-supply, 4-bit voltage translator / isolator / for open-d rain and push-pull applications v ol vs. i ol the i 2 c specification mandates a maximum v il (i ol of 3ma) of v cc ? 0.3 and a maximum v ol of 0.4v. if there is a master on the a port of an i 2 c translator with a v cc of 1.65v and a slave on the i 2 c translator b port with a v cc of 3.3v, the maximum v il of the master is (1.65v x 0.3) 495mv. the slave could legally transmit a valid logic low of 0.4v to the master. if the i 2 c translator?s channel resistance is too high, the voltage drop across the translator could present a v il to the master greater than 495m v. to complicate matters, the i 2 c specification stat es that 6ma of i ol is recommended for bus capacitances approaching 400pf. more i ol increases the voltage drop across the i 2 c translator. the i 2 c application benefits when i 2 c translators exhibit low v ol performance. figure 5 depicts typical fxmar2104 v ol performance vs. a competitor, given a 0.4v v il . figure 5. v ol vs. i ol
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 8 fxmar2104 ? dual-supply, 4-bit voltage translator / isolator / for open-d rain and push-pull applications i 2 c bus isolation the fxmar2104 supports i 2 c-bus ? isolation for the following conditions: ? bus isolation if bus clear ? bus isolation if either v cc goes to ground bus clear because the i 2 c specification defines the minimum scl frequency of dc, the scl signal can be held low forever; however, this condition shuts down the i 2 c bus. the i 2 c specification refers to this condition as bus clear. in figure 6, if slave #2 holds down scl forever, the master and slave #1 are not able to communicate because the fxmar2104 passes the scl stuck-low condition from slave #2 to slave #1 as well as the master. however, if the oe pin is pulled low (disabled), both ports (a a nd b) are 3-stated. this results in the fxmar2104 is olating slave #2 from the master and slave #1, allowing full communication between the master and slave #1. either v cc to gnd if slave #2 is a camera that is suddenly removed from the i 2 c bus, resulting in v ccb transitioning from a valid v cc (1.65v ? 5.5v) to 0v; the fxmar2104 automatically forces all i/os on both its a and b ports into 3-state. once v ccb has reached 0v, full i 2 c communication between the master and slave #1 remains undisturbed. figure 6. bus isolation
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 9 fxmar2104 ? dual-supply, 4-bit voltag e translator / isolator / for open -drain and push-pull applications dc electrical characteristics t a = ?40c to +85c. symbol parameter condition v cca (v) v ccb (v) min. typ. max. unit v iha high level input voltage a data inputs a n 1.65-5.50 1.65-5.50 v cca ? 0.4 v control input oe 1.65- 5.50 1.65-5.50 0.7 x v cca v ihb high level input voltage b data inputs b n 1.65-5.50 1.65-5.50 v ccb ? 0.4 v v ila low level input voltage a data inputs a n 1.65-5.50 1.65-5.50 0.4 v control input oe 1.65-5.50 1.65-5.50 0.3 x v cca v ilb low level input voltage b data inputs b n 1.65-5.50 1.65-5.50 0.4 v v ol low level output voltage v il = 0.15v 1.65-5.50 1.65-5.50 0.4 v i ol = 6ma i l input leakage current control input oe, v in = v cca or gnd 1.65-5.50 1.65-5.50 1 a i off power-off leakage current a n v in or v o = 0v to 5.5v 0 5.50 2 a b n v in or v o = 0v to 5.5v 5.50 0 2 i oz 3-state output leakage (6) a n , b n v o = 0v to 5.5v, oe = v il 5.50 5.50 2 a a n v o = 0v to 5.5v, oe = don?t care 5.50 0 2 b n v o = 0v to 5.5v, oe = don?t care 0 5.50 2 i cca / b quiescent supply current (7,8) v in = v cci or floating, i o = 0 1.65-5.50 1.65-5.50 5 a i ccz quiescent supply current (7) v in = v cci or gnd, i o = 0, oe = v il 1.65-5.50 1.65-5.50 5 a i cca quiescent supply current (6) v in = 5.5v or gnd, i o = 0, oe = don?t care, b n to a n 0 1.65-5.50 -2 a 1.65-5.50 0 2 i ccb quiescent supply current (6) v in = 5.5v or gnd, i o = 0, oe = don?t care, a n to b n 1.65-5.50 0 -2 a 0 1.65-5.50 2 r pu resistor pull-up value v cca & v ccb sides 1.65-5.50 1.65-5.50 10 k notes: 5. this table contains the ou tput voltage for static conditions. dynamic driv e specifications are given in the dynamic output electrical characteristics. 6. ?don?t care? indicates any valid logic level. 7. v cci is the v cc associated with the input side. 8. reflects current per supply, v cca or v ccb .
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 10 fxmar2104 ? dual-supply, 4-bit voltag e translator / isolator / for open -drain and push-pull applications dynamic output electr ical characteristics output rise / fall time output load: c l = 50pf, r pu = nc, push-pull driver, and t a = -40c to +85c. symbol parameter v cco (10) unit 4.5 to 5.5v 3.0 to 3.6v 2.3 to 2.7v 1.65 to 1.95v typical t rise output rise time; a port, b port (11) 3 4 5 7 ns t fall output fall time; a port, b port (12) 11 8 6 4 ns notes: 9. output rise and fall times guaranteed by design si mulation and characterization; not production tested. 10. v cco is the v cc associated with the output side. 11. see figure 11 . 12. see figure 12 . maximum data rate ( 13 ) output load: c l = 50pf, r pu = nc, push-pull driver, and t a = -40c to +85c. v cca direction v ccb unit 4.5 to 5.5v 3.0 to 3.6v 2.3 to 2.7v 1.65 to 1.95v minimum 4.5v to 5.5v a to b 26 20 16 9 mhz b to a 26 20 16 9 3.0v to 3.6v a to b 26 20 16 9 mhz b to a 26 20 16 9 2.3v to 2.7v a to b 26 20 16 9 mhz b to a 26 20 16 9 1.65v to 1.95v a to b 26 20 16 9 mhz b to a 26 20 16 9 note: 13. f-toggle guaranteed by design simulation; not production tested.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 11 fxmar2104 ? dual-supply, 4-bit voltag e translator / isolator / for open -drain and push-pull applications ac characteristics (17) output load: c l = 50pf, r pu = nc, push-pull driver, and t a = -40c to +85c. symbol parameter v ccb unit 4.5 to 5.5v 3.0 to 3.6v 2.3 to 2.7v 1.65 to 1.95v typ. max. typ. max. typ. max. typ. max. v cca = 4.5 to 5.5v t plh a to b 1 3 1 3 1 3 1 3 ns b to a 1 3 2 4 3 5 4 7 t phl a to b 2 4 3 5 4 6 6 7 ns b to a 2 4 2 5 2 6 5 7 t pzl oe to a 4 5 6 10 5 9 7 15 ns oe to b 3 5 4 7 5 8 10 15 t plz oe to a 65 100 65 105 65 105 65 105 ns oe to b 5 9 6 10 7 12 9 16 t skew a port, b port (14) 0.5 1.5 0.5 1.0 0. 5 1.0 0.5 1.0 ns v cca = 3.0 to 3.6v t plh a to b 2.0 5.0 1.5 3.0 1.5 3.0 1.5 3.0 ns b to a 1.5 3.0 1.5 4.0 2.0 6.0 3.0 9.0 t phl a to b 2.0 4.0 2.0 4.0 2.0 5.0 6.0 7.0 ns b to a 2.0 4.0 2.0 4.0 2.0 5.0 3.0 5.0 t pzl oe to a 4.0 8.0 5.0 9.0 6.0 11.0 7.0 15.0 ns oe to b 4.0 8.0 6.0 9.0 8.0 11.0 10.0 14.0 t plz oe to a 100 115 100 115 100 115 100 115 ns oe to b 5 10 4 8 5 10 9 15 t skew a port, b port (14) 0.5 1.5 0.5 1.0 0. 5 1.0 0.5 1.0 ns v cca = 2.3 to 2.7v t plh a to b 2.5 5.0 2.5 5.0 2.0 4.0 1.0 3.0 ns b to a 1.5 3.0 2.0 4.0 3.0 6.0 5.0 10.0 t phl a to b 2 5 2 5 2 5 5 6 ns b to a 2 5 2 5 2 5 3 6 t pzl oe to a 5.0 10.0 5.0 10.0 6.0 12.0 90.0 18.0 ns oe to b 4.0 8.0 4.5 9.0 5.0 10.0 9.0 18.0 t plz oe to a 100 115 100 115 100 115 100 115 ns oe to b 65 110 65 110 65 115 12 25 t skew a port, b port (14) 0.5 1.5 0.5 1.0 0. 5 1.0 0.5 1.0 ns v cca = 1.65 to 1.95v t plh a to b 4.0 7.0 4.0 7.0 5.0 8.0 5.0 10.0 ns b to a 1.0 2.0 1.0 2.0 1.5 3.0 5.0 10.0 t phl a to b 5 8 3 7 3 7 8 9 ns b to a 4 8 3 7 3 7 3 7 t pzl oe to a 11 15 11 14 14 28 14 23 ns oe to b 6 14 6 14 6 14 9 19 t plz oe to a 75 115 75 115 75 115 75 115 ns oe to b 75 115 75 115 75 115 75 115 t skew a port, b port (14) 0.5 1.5 0.5 1.0 0.5 1.0 0.5 1.0 ns note: 14. skew is the variation of propagatio n delay between output signals and applies only to output signals on the same port (a n or b n ) and switching with the same polarity (low-to-high or high-to-low) (see figure 14) . skew is guaranteed, but not tested. 15. ac characteristic is guaranteed by design and characterization
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 12 fxmar2104 ? dual-supply, 4-bit voltag e translator / isolator / for open -drain and push-pull applications capacitance t a = +25c. symbol parameter condition typical unit c in input capacitance control pin (oe) v cca = v ccb = gnd 2.2 pf c i/o input/output capacitance, a n , b n v cca = v ccb = 5.0v, oe = gnd 13.0 pf figure 7. a c test circuit table 1. propagation delay table (16) test input signal output enable control t plh , t phl data pulses v cca t pzl (oe to a n , b n ) 0v low to high switch t plz (oe to a n , b n ) 0v high to low switch note: 16. for t pzl and t plz testing, an external 2.2k pull-up resistor to v cco is required to force the i/o pins high while oe is low. when oe is low, the internal 10k rpus are decoupled from their respective v cc ?s. table 2. ac load table v cco c l r l 1.8 0.15v 50pf nc 2.5 0.2v 50pf nc 3.3 0.3v 50pf nc 5.0 0.5v 50pf nc
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 13 fxmar2104 ? dual-supply, 4-bit voltag e translator / isolator / for open -drain and push-pull applications timing diagrams figure 8. waveform for inverting and non-inverting functions (17) figure 9. 3-state output low enable time ( 17 ) symbol v cc v mi v cci / 2 v mo v cco / 2 v x 0.5 x v cco v y 0.1 x v cco figure 10. 3-state output high enable time (17) figure 11. active output rise time figure 12. a ctive output fall time figure 13. f-toggle rate figure 14. output skew time notes: 17. input t r = t f = 2.0ns, 10% to 90% at v in = 1.65v to 1.95v; input t r = t f = 2.0ns, 10% to 90% at v in = 2.3 to 2.7v; input t r = t f = 2.5ns, 10% to 90%, at v in = 3.0v to 3.6v only; input t r = t f = 2.5ns, 10% to 90%, at v in = 4.5v to 5.5 only. 18. v cci = v cca for control pin oe or v mi = (v cca / 2). v cci v cco gnd data in data out t pxx t pxx v mi v mo data out output control t pzl v mi v cc a v ol gnd v y data out output control t plz v mi v cca v ol gnd v x v cci v cci /2 v cci /2 gnd data in t period f-toggle rate, f = 1 / t period v cco v mo t skew t skew v mo gnd data output t skew = (t phlmax ? t phlmin ) or (t plhmax ? t plhmin ) v cco v mo v mo gnd data output
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 14 fxmar2104 ? dual-supply, 4-bit voltag e translator / isolator / for open -drain and push-pull applications physical dimensions figure 15. 12-lead ultrat hin mlp, 1.8mm x 1.8mm package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . a b c seating plane recommended land pattern notes: a. package does not fully conform to jedec standard. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. land patter n recommendation is based on fsc design only. e. drawing filename: mkt-umlp12arev4. scale : 2x lead option 1 scale : 2x lead option 2 detail a scale : 2x pin#1 ident top view bottom view 0.10 c 0.08 c 0.10 c 2x 2x side view 0.10 c 0.05 0.00 3 6 1 0.10 cab 0.05 c 0.55 max. 12 1.80 1.80 0.40 0.25 0.15 (12x) 0.35 0.45 2.10 2.10 0.40 0.563 (11x) 0.20 (12x) 1 0.152 9 0.588 detail a pin#1 ident (11x) package edge 0.10 0.10 0.45 0.35 0.10
? 2011 fairchild semiconductor corporation www.fairchildsemi.com fxmar2104 ? rev. 1.0.1 15 fxmar2104 ? dual-supply, 4-bit voltag e translator / isolator / for open -drain and push-pull applications

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